FPGA Case Study

A multinational corporate approached Bluewater Systems to implement an in-house custom bus in an FPGA design. The bus was used in telecoms technology to communicate between various components. Unfortunately the only available documentation was a pinout for the bus. No information was available concerning the bus cycles or even pin direction.

To test our design, we were presented with a piece of (fairly antiquated) hardware which used the bus. The challenge was to control this hardware successfully, using it to read, write and store data.

OUR APPROACH
Since very little documentation was available, we planned to use a Logic Analyser to probe the bus and watch it in operation. By making educated guesses about the purpose of each pin, and the types of bus transactions supported by the bus, we should be able to write a priliminary specification for the bus.

This was a somewhat risky and uncertain approach, and a very unusual way of undertaking an FPGA design. However, with limited documentation there was no choice but to reverse-engineer the supplied hardware.

DEVELOPMENT
Using the basic bus specification, we produced a prototype connector board for our in-house Integrator CM-XA10 platform.

An FPGA design was produced to handle the bus transactions as we understood them. The design was made very configurable, particularly with regard to timing, to allow it to be used for probing as well as driving the bus.

The prototype was then connected to the bus while traffic was flowing. After a few tweaks we were able to make the FPGA prototype 'understand' most of the bus traffic, and we were able to write a detailed specification for the bus.

Armed with this specification and a slightly enhanced prototype, we developed a software program to drive the bus and control the supplied peripheral. Using this we were able to write data to the peripheral and read it back again later.

From this, the FPGA design was cut back to the minimum functionality needed to understand and drive the bus. This resulted in considerable logic size savings with no loss in features. The software program was turned into a driver for the chosen Operating System, and the project proceeded rapidly towards a conclusion.

THE OUTCOME
The final design was able to operate on the bus as required and in fact used a relatively small amount of logic. Cost pressures were not particularly strong, so a fairly large FPGA was chosen and FIFO sizes were increased to take advantage of the extra FPGA space.